SMART Group

The SMART Group Flip Chip Assembly and Underfill seminar was conducted at Speedline Technology in Reading with over thirty people in attendance during the day. Presentations were given on board requirements, design, assembly, soldering and underfiling both Flip Chip and Chip Scale Package. This is the fourth flip chip event run by Speedline in the UK and France, but the first specifically run with the SMART.

Example of flip chip underfilled device

Presenters included:

Bruce Seaton - Speedline
Jason Pye - Speedline
Dr Aisling Lakes - Loctite/Multicore
Bob Willis - SMART Group

Bruce Seaton gave an excellent overview of the technology and the processes surrounding flip chip and its uses in current technology. He illustrated the benefits and issues as he had done in November at the SMART Group European Conference and voted one of the best sessions at the conference.

Jason Pye concentrated on the process of underfill, the materials and design requirements for the process. He illustrated how to calculate the amount of material for different parts and what can affect the reliability of the process during his practical underfilling demonstrations. Aisling Lakes of Loctite focused on the materials illustrating the process guidelines of material selection and what can be achieved in terms of reliability of joints which are subject to thermal cycling. She also highlighted the trend in underfuilling CSP parts which is not related to thermal failures but due to mechanical strain on parts. This is particularly seen on phones, hand held computers subjected to shock, flexure and bending during use and assembly.

Picture of Delegates during the practical hands on session

During the afternoon session delegates had the opportunity to see test boards being undefiled and cured and parts being removed to examine the results of the process. The seminar was a mixture of technical presentations and practical work which made up a enjoyable day for all the delegates and speakers. Although not used on the day, presentations covered the results of recent process trials using X-ray and SCAN to examine solder joint reflow and underfill voiding. As well as papers presented delegates also received a number of other papers on CD-ROM covering underfil materials and flip chip placement.

Example of laminate flip chips produced specifically for the Speedline Seminar

For copies of all the flip chip papers presented and some that were not on CD-ROM contact Tony Gordon info@smartgroup.org

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